1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and more particularly to a semiconductor integrated circuit device for constituting a CMOS logic circuit capable of driving a high voltage without an additional thick oxide film step in a CMOS unit manufacturing process by using a transistor of a low voltage type.
2. Description of the Related Art
The microfabrication of a semiconductor integrated circuit device using a CMOS transistor has been advanced and the degree of integration has been increased more and more. With the microfabrication, the supply voltage of the semiconductor integrated circuit device is dropped in accordance with the scaling rule. For example, in a 0.18 μm process, the standard working voltage of a standard MOS transistor is standard 1.8V, and a MOS transistor having a gate oxide film thickness of approximately 4 nm is used. Most of units to be used in the semiconductor integrated circuit device in the 0.18 μm process are semiconductor devices using a circuit utilizing a MOS transistor having a 1.8V specification and having the degree of integration increased. In a whole system, a semiconductor integrated circuit device having a 3.3V specification created in a former process is mixed or the driving voltage of a motor or an LCD cannot be dropped in some components. In a connection to the components, a breakdown voltage cannot be obtained in the transistor having the 1.8V specification. For this reason, it is necessary to further prepare, as a separate process, a MOS transistor having a high voltage specification for driving a high voltage.
The following needs the care. In the case in which a voltage system transistor of a new type is to be introduced, it is necessary to introduce a transistor having a film thickness corresponding to the voltage system. For example, in the 0.18 μm process, there is provided a transistor having a 3.3V specification in the thickness of the gate oxide film of approximately 8 nm which drives 3.3 V of the semiconductor integrated circuit device (0.35 μm process) created in the former process described above. The 8 nm gate oxide film is generally formed by a method referred to as a double oxidation and the whole Si surface of a portion in which the transistor is formed is once oxidized at a gate oxide film forming step to form an oxide film having a certain thickness, and only the oxide film in the portion in which a transistor having a 1.8 V specification is formed is etched, and thereafter, the whole surface is further oxidized, which will not be described in detail. Therefore, the oxide film of the transistor having the 3.3 V specification is formed by the oxidation carried out twice which puts an etching step therebetween. In the case in which a high voltage transistor of another type is further required, a triple gate oxide film is formed.
There is the following problem. More specifically, the double and triple gate oxide films have variations in thicknesses increased. In addition, in a transistor having a kind of thinnest oxide film, the etching step is carried out so that an increase in a diffusion length is caused by a variation in a channel concentration and an impurity diffusion due to a heating step of forming an oxide film and it is hard to form and control a transistor having a very small dimension.
In other words, it is difficult to carelessly increase the type of a transistor having a working voltage corresponding to a voltage to be used. Due to this restriction, a voltage which can be used in the semiconductor integrated circuit device is limited. For such a problem, there has been proposed a semiconductor integrated circuit device using a CMOS transistor handling a signal having a higher supply voltage by utilizing a transistor of a low voltage type (for example, see U.S. Pat. No. 5,465,054 and Japanese Patent No. 3190915).
FIG. 8 shows a semiconductor integrated circuit device using a CMOS transistor handling a signal having a higher supply voltage by utilizing a transistor of a low voltage type. An input signal IN is given to the gate of an N-type transistor M102 connected to GND through an N-type transistor and transfer gate M101 having a gate to which a shielding voltage VSHLD is applied, while the input signal IN is given to the gate of a P-type transistor M104 connected to a power supply VDD through a P-type transistor and transfer gate M103 having a gate to which the shielding voltage VSHLD is applied, and the drains of the N- and P-type transistors M102 and M104 are connected to an output terminal OUT through transfer gates M105 and M106 having gates to which the shielding voltage VSHLD is applied, respectively.
The composite unit logically serves as a CMOS inverter and has an allowable voltage which is approximately a double of that of each unit.
(1) Referring to the Breakdown Voltage of a Gate Oxide Film
In case of the N-type transistor M102 to be the main component of a CMOS inverter, a voltage which is equal to or higher than a voltage of the shielding voltage VSHLD−threshold voltage Vtn which is the gate voltage of the N-type transistor and transfer gate M101 connected to a gate thereof is not applied, and a voltage which is equal to or higher than the former voltage (the shielding voltage VSHLD−threshold voltage Vtn) is not applied even if a supply voltage VDD having a logical level in a circuit with a VDD system power supply is applied. When the shielding voltage VSHLD is set to be approximately VDD/2, moreover, only a voltage which is equal to or lower than the breakdown voltage of the N-type transistor is applied to the gate of the N-type transistor M102 even if a double of the breakdown voltage is applied as the supply voltage VDD. Referring to the N-type transistor and transfer gate M101, furthermore, a voltage of VDD/2 is applied to the gate itself. Even if a signal having an amplitude on supply voltage VDD and GND levels is input to the input terminal IN, therefore, only a half of the supply voltage is applied as a stress to a gate oxide film. Referring to the P-type transistors M104 and M103, similarly, only a half of the supply voltage is applied as the stress. Also in a general system having a supply voltage which is a double of a breakdown voltage, therefore, a composite unit having such a structure can satisfy the breakdown voltage of the gate oxide film and a deterioration in the reliability of the gate oxide film can be avoided.
In addition, the argument about the breakdown voltage of the gate oxide film applies to all transistors including the drain voltage limiting transistors M105 and M106.
(2) A Drain-Source Breakdown Voltage (a Channel Breakdown Voltage)
The N-type transistor M102 to be the main component of the CMOS inverter has a source connected to the GND and a drain connected to the output terminal OUT for outputting a voltage of the supply voltage VDD-GND through the N-type transfer gate transistor M105 having the gate to which the shielding voltage VSHLD is input. The drain voltage of the N-type transistor M102 has an upper limit voltage which is limited by the N-type transfer gate M105 and is lower than the shielding voltage VSHLD-threshold voltage Vtn, and the shielding voltage VSHLD is a half of the supply voltage VDD. For this reason, a voltage to be applied to the drain of the N-type transistor M102 can be prevented from exceeding the half of the supply voltage VDD. Even if a double of the N-type transistor breakdown voltage is applied as the supply voltage VDD in the same manner as in the argument, therefore, only a voltage which is equal to or lower than the breakdown voltage is applied as the drain-source voltage of the N-type transistor M102. Referring to other N-type transistors (the two N-type transfer gates M101 and M105), consequently, it is possible to maintain the drain-source voltage to be equal to or lower than the breakdown voltage by properly holding the transition speed of the input signal IN and the size of a device. Furthermore, this applies to the P-type transistors M104, M103 and M106.
Although it is possible to drive a high voltage by using a transistor of a low voltage type in the technique as described above, there are the following problems.
(1) A transfer gate transistor for an increase in a voltage is added to a current path for driving an output and they are connected in series. For this reason, an extra transistor arrangement is required. Consequently, the size of a driver is increased by double causes.
(2) When the supply voltage VDD is set to be equal to or higher than a double of the breakdown voltage of each unit, a voltage to be applied to each unit is equal to or higher than the breakdown voltage. With the conventional structure, therefore, the supply voltage VDD cannot be increased to be a double of the breakdown voltage of the unit or more.